The present invention relates to a monolithic semi-custom LSI having a plurality of standard LSI logic sections, each of which is capable of functioning as an independent LSI having a predetermined logic configuration and wiring pattern, a gate array constituting a peripheral circuit of the standard LSI logic sections, and a mask ROM for controlling the logic sections and the gate array.
LSI design techniques represented by a gate array design technique have been simplified. By using these techniques, LSI system design, conventionally confined to semiconductor engineers, can now be easily performed by engineers in other fields. Thus, more systems utilizing LSIs and low-profile compact systems are being developed.
Microcomputers and their LSI family have become popular, and miscellaneous circuits, called glue circuits, which are separate from microcomputers and their peripheral LSI family, are now subject to LSI configuration. This is because a large-scale circuit such as a microcomputer or its LSI family cannot be incorporated in a gate array or a standard cell. The most compact hardware configuration of a logic circuit is given by a system of "microcomputer+peripheral family chips+gate arrays or standard cells". It is difficult to achieve further integration and compactness of logic circuits.
FIG. 1 is a block diagram showing a system configuration in accordance with a conventional LSI technique. Functional blocks 30 through 69 are constituted by independent logic elements (i.e., semiconductor chips).
The system of FIG. 1 has a CPU 30, oscillators 31A and 50A, a clock generator (C-G) 31B, a bus controller (BUS-CONT) 32, DMA controllers (DMA-CONT) 33 and 34, latches (LATCH) 35, 40, 47, 48 and 54; a timer (TMR) 36, an interrupt controller (PIC) 37, mask ROMs (MROM) 38 and 45, a RAM 39, dynamic RAMs (D-RAM) 41 and 46, a D-RAM controller (DRAM-CONT) 42, glue circuits 43 and 49, a CRT miscellaneous circuit (GA-CRT) 43 and a CPU miscellaneous circuit (GA-CPU) 49 constituted respectively by gate arrays (GA), a CRT controller (CRTC) 44, a PLL circuit (PLL) 50B, a floppy disk controller (FDC) 51, a floppy disk interface (FDD-IF) 52, a register (REG) 53, a video driver (VIDEO-OUTPUT) 55, drivers (DRV) 57, 58, 59, 60 and 63; a parity generator (PAR-G) 61, drivers/receivers (D/R) 62, 64, 65, 66 and 67; a keyboard/speaker interface (KB-SPK-SW) 68, a numerical data processor 69, and connector pin junctions PJ1, PJ2, and PJ4 through PJ11. Chip model numbers are indicated in parentheses in FIG. 1.
In a conventional system, since the functional circuits 30 through 69 are constituted respectively by independent logic circuit elements (semiconductor chips), design flexibility can be achieved to some extent, but system hardware can be made neither compact nor simplified, resulting in inconvenience.